1. Field of the Invention
The invention relates to a phase-locked loop with a phase detector, a loop filter and an oscillator connected in series.
In a phase-locked loop (PLL), an oscillator is synchronized to the phase of an input signal. The basic configuration of a PLL is known, for instance, from the book by Tietze and Schenk, entitled: Electronic Circuits, 1991, especially FIG. 27.20.
The characteristic variables of a PLL are its natural frequency and its damping. In a PLL constructed in the form of integrated circuits, those variables are dependent on the technology, among other factors, and can accordingly fluctuate over a range of about .+-.50%. Those inaccuracies, for instance in frequency synthesis with PLL, lead to increased jitter or instability of the circuit. The critical point in that case is the damping. The damping should be at least 0.7 in order to assure the stability of the PLL. With the usual technology-dependent tolerances, the damping would have to be oversized to from 2 to 4 times the normal value.
One approach for solving that problem in the prior art is known, for instance, from U.S. Pat. No. 5,491,439. FIG. 1 of that patent indicates a PLL of that generic type. After the operating point has been adjusted, the damping is lowered by current switchover, which leads to a reduced amount of jitter.